Develop custom IP for new features of the SDR and digital payload
Iterate on current DSP and interface designs to improve reliability
Work with IP core vendors to integrate new functionality into the SDR
Work with lead engineers in developing the communications and network architecture of our future satellite constellation
Participate in conceptual design studies of new spacecraft
Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent
5+ yr. working experience with FPGA/RTL design
Verilog, SystemVerilog, or VHDL
Xilinx FPGA(s). Specifically, Zynq and UltraScale
Solid understanding of timing principles, including clock domain crossing and timing closure
Strong scripting skills (e.g Python, Tcl, csh/bash, etc.)
Experience with FPGA tools (e.g Vivado, Quartus), HDL Simulation Tools (ModelSim)
Masters of Science in Computer/Electrical Engineering, or equivalent
Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM
Experience with memory mapped interfaces such as AXI, Wishbone, Avalon
Experience with high-speed transceivers for protocols such as JESD204B, PCIe, SATA
Experience designing printed circuit boards
Knowledge of radio-frequency electronics design