FPGA verification using different verification methods and tools, such Modelsim, Vivado, JTAG or real time test on target.
HDL implementation of different DSP methods such as tracking loop, correlator, digital filter, AGC or FFT
HDL implementation of different IO, such as SPI, UART, I2C and ARINC
Integrating the FPGA or ASIC with embedded software on a CPU or with analog circuits, such as attenuator or synthesizer
Good experience in verifying complex digital systems.
Experience developing requirements-based verification plans, UVM test benches and test cases (SystemVerilog + UVM, Tcl, Ruby, and Python) using Siemens QuestaSim (targeting Questasim 2021.1 or newer)
Experience with test development for HDL simulation and target test verification platforms using Xilinx Series 7 and UltraScale+ MPSoC FPGAs
Prior verification work on a minimum of three DSP related devices
Demonstrated prior experience verifying Digital Signal Processor (DSP) elements, correlators, Programmable Half-band and FIR filters, Automatic Gain Control, ADC processing
Developing UVM test environments that support both HDL simulation and FPGA target testing of DSP for Global Navigation Satellite System DSP (GPS, Galileo; both L1 & L5 signals); Pseudo Random Number (PRN) using Linear Feedback Shift Registers (LFSR) generators, Timer chains, Distribution bins, Carrier Phase Generators, Numerically Controlled Oscillators (NCOs) and Mixers.
Ability to generate new, or update existing, documentation (test plans, test cases, test procedures) in English
Participate in peer reviews of own work as author and that of others as tester
Familiar with Amba AHB and APB bus protocols
A ‘nice to have’ would be familiarity with IBM Rational DOORS and Integrity LM Client (MKS)